1. Field of the Invention
The present invention relates to methods for manufacturing metal-oxide semiconductor (MOS) transistors utilizing a hybrid hard mask, and more particularly, to methods for manufacturing MOS transistors with a selective epitaxial growth (SEG) method.
2. Description of the Prior Art
Selective epitaxial growth (SEG) technology is used to form an epitaxial silicon layer on a single-crystalline substrate, in which the crystalline orientation of the epitaxial silicon layer is almost identical to that of the substrate. SEG technology is widely applied in manufacturing numerous kinds of semiconductor devices, such as MOS transistors having raised source/drain regions which benefits from good short channel character and low parasitical resistance and a MOS transistor having recessed source/drain which improves drain induced barrier lowering (DIBL) and punchthrough effect and reduces off-state current leakage and power consumption.
Generally, SEG technology includes performing a cleaning process to remove native oxides and other impurities from a surface of a substrate, then depositing an epitaxial silicon layer on the substrate and making the epitaxial silicon layer grow along with the silicon lattice of the substrate. Please refer to FIGS. 1-4, which are schematic drawings illustrating a conventional method for manufacturing a MOS transistor with SEG technology. As shown in FIG. 1, a substrate 100 such as a silicon substrate having a plurality of shallow trench isolations (STI) 102 formed thereon on is provided. A dielectric layer 112, a polysilicon layer 114, and a hard mask layer comprising silicon nitride or silicon oxide are sequentially formed on the substrate 100. The hard mask layer is patterned by a lithography process and the patterned hard mask layer 120 is used to define a position and a length of a gate.
Please refer to FIG. 2. Then, an etching process is performed to remove portions of the polysilicon layer 114 and the dielectric layer 112, thus a gate 110 is formed. Next, an ion implantation process is performed to form lightly doped drains (LDDs) 116 in the substrate 100 respectively at two sides of the gate 110, and a spacer 118 is formed on sidewalls of the gate 110. Please refer to FIGS. 3-4. The patterned hard mask layer 120 and the spacer are used to be an etching mask in an etching process to form recesses 130 in the substrate 100 at the two sides of the gate 110. As shown in FIG. 4, then an epitaxial silicon layer 132 is formed along surface of the substrate 100 in the recesses 130 by a SEG process. In addition, an ion implantation process is performed before etching the recesses 130 or after forming the epitaxial silicon layer 132 to complete formation of the recessed source/drain.
It is noteworthy that the substrate 100 will undergo many etching or cleaning processes after forming the gate 100 and before performing the SEG process, for example, a cleaning process after etching the polysilicon layer 114, a cleaning process after forming the LDDs 116, the spacer 118 etching and cleaning processes, the recesses 130 etching and cleaning processes, and cleaning process before the SEG process. Those cleaning or etching processes repeatedly consume the patterned hard mask layer 120 covering the polysilicon layer 114. Such exposure is usually and easily happened on corners of the patterned hard mask 120. Therefore the polysilicon layer 114 may be exposed before performing the SEG process due to the consumption of the patterned hard mask layer 120. It is known that the epitaxial silicon layer 132 grows on all exposed silicon surfaces, and the epitaxial silicon layer 132 grown on the source and drain regions are desirable while the epitaxial silicon layer 132 grown on the gate 110 is undesirable because the growth causes dopants in the gate 110 to diffuse into the newly grown epitaxial silicon, and thus results in a decrease in gate activation or an increase in the gate inversion, which leads to degradation of the device performance. Furthermore, the undesirably grown epitaxial silicon layer 132 on the gate 110 makes it possible to form a link of conductive silicon from the gate 110 over the spacer 118 to the source/drain in the following processes and causes short circuit.
In addition, the patterned hard mask layer 120 comprising silicon nitride is uneasy to be removed. Removal of the patterned hard mask layer 120, exemplary removal of the patterned hard mask layer 120 for forming a salicide on the surface of the polysilicon layer 114, usually damages profile of the gate 110. More undesirably, the spacer 118 may be removed together with the patterned hard mask layer 120 and thus the damage extends to the sidewalls of the gate 110 or the dielectric layer 112 underneath the polysilicon layer 114.
Therefore a hard mask layer effectively resisting consumption during the cleaning and etching processes and that is easily removed without damaging other elements is in need of an immediate solution.